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1 the lt c ? 3255 is a switched-capacitor step-down dc/dc converter that produces a regulated output (2.4v to 12.5v adjustable) from a 4v to 48v input. in applications where the input voltage exceeds twice the output voltage , 2:1 capacitive charge pumping extends output current capabil - ity beyond input supply current limits. at no load, burst mode ? operation cuts v in quiescent current to 16a. with its integrated v in shunt regulator, the LTC3255 excels in 4ma to 20ma current loop applications. the device enables current multiplication; a 4ma input current can power a 7.4ma load continuously. alternatively, the LTC3255 serves as a higher efficiency replacement for linear regulators and provides a space-saving inductor- free alternative to buck dc/dc converters. the LTC3255 withstands reverse-polarity input supplies and output short- circuits without damage. safety features including current limit and overtemperature protection further enhance robustness. the LTC3255 is available in thermally enhanced 10-lead msop and low profile 3mm 3mm 10-lead dfn packages. typical application features description wide v in range fault protected 50ma step-down charge pump 7.4ma dc supply from 4ma to 20ma current loop applications n input voltage range: 4v to 48v n adjustable regulated output: 2.4v to 12.5v n output current: 50ma maximum n 16 a quiescent current in regulation at no load n input fault protection from C52v to 60v n multimode charge pump (2:1, 1:1) with automatic mode switching maintains regulation over wide v in range n input voltage shunt mode for current- fed applications n power good output n overtemperature and short- circuit protection n operating junction temperature: 150c maximum n thermally enhanced 10-lead msop and 10-lead (3mm 3mm) dfn packages n industrial control, factory automation, sensors, and scada systems n housekeeping power supplies n current-boosting voltage regulators for 4ma to 20ma current loops l, lt , lt c , lt m , linear technology , the linear logo and burst mode are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. v in en 220k 10f 3255 ta01a 0.1f 4ma to 20ma input >10v compliance 1f 1f output 3.3v 7.4ma LTC3255 gnd c + c ? shunt bias pgood + ? pgood fb v out 2.15m 1.21m available output current vs input current 4 8 12 14 20 6 10 16 18 input current (ma) available output current (ma) 16 31 34 37 40 10 25 13 28 7 4 22 19 3255 ta01b increased i out capability available i out input current ltc 3255 3255f for more information www.linear.com/LTC3255
2 pin configuration absolute maximum ratings v in , en ........................................................ C52 v to 60 v v out .......................................................................... 15 v v out short - circuit duration ( note 6) ............... indefinite i vout when v out < 0 v ( note 4) ............................. 50 ma fb ............................................................................. 6 v pgood ...................................................................... 15 v (notes 1, 2) top view 11 gnd dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v in c ? gnd bias en c + v out fb shunt pgood t jmax = 150c, v ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 c + v out fb shunt pgood 10 9 8 7 6 v in c ? gnd bias en top view 11 gnd mse package 10-lead plastic msop t jmax = 150c, v ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC3255edd#pbf LTC3255edd#trpbf lghd 10-lead (3mm w 3mm) plastic dfn C40c to 125c LTC3255idd#pbf LTC3255idd#trpbf lghd 10-lead (3mm w 3mm) plastic dfn C40c to 125c LTC3255hdd#pbf LTC3255hdd#trpbf lghd 10-lead (3mm w 3mm) plastic dfn C40c to 150c LTC3255mpdd#pbf LTC3255mpdd#trpbf lghd 10-lead (3mm w 3mm) plastic dfn C55c to 150c LTC3255emse#pbf LTC3255emse#trpbf ltghf 10-lead plastic msop C40c to 125c LTC3255imse#pbf LTC3255imse#trpbf ltghf 10-lead plastic msop C40c to 125c LTC3255hmse#pbf LTC3255hmse#trpbf ltghf 10-lead plastic msop C40c to 150c LTC3255mpmse#pbf LTC3255mpmse#trpbf ltghf 10-lead plastic msop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ i pgood when v pgood < 0 v ( note 5) ..................... 100 a operating junction temperature range ( notes 3, 6) ................................. C55 c to 150 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) mse only .......................................................... 300 c ltc 3255 3255f for more information www.linear.com/LTC3255
3 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v unless otherwise noted. (notes 2, 3) electrical characteristics symbol parameter conditions min typ max units v in input voltage range (note 7) l 4 48 v v out output voltage range l 2.4 12.5 v v uvlo_bk v in undervoltage lockout threshold with shunt disabled v in rising, shunt = gnd hysteresis, shunt = gnd 2.4 50 2.7 v mv v uvlo_sh v in undervoltage lockout threshold with shunt enabled v in rising, shunt= bias hysteresis, shunt= bias 5 200 5.7 v mv i vin v in quiescent current en low en high, shunt = gnd en high, shunt = bias shutdown enabled, output in regulation enabled, output in regulation 3 16 30 6 35 45 a a a i vout available output current shunt disabled shunt enabled shunt = gnd shunt = bias, i vin = 4ma, v out = 3.3v l l 50 7.4 7.8 ma ma v fb regulated feedback voltage l 1.176 1.200 1.224 v i fb fb pin leakage v fb = 1.3v 10 na v en_vih en high level input voltage l 1.4 v v en_vil en low level input voltage l 0.4 v i en en pin input current v en = 12v v en = 0v 0 0 1 1 a a i lim v out current limit 120 ma f osc oscillator frequency 500 khz v pgthresh pgood rising threshold % of final regulation voltage l 90 94 98 % v pg(low) pgood output low voltage i pgood = 200a 0.1 0.4 v pgood high impedance leakage v pgood = 12v l 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are referenced to gnd unless otherwise specified. note 3: the LTC3255e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3255i is guaranteed over the C40c to 125c operating junction temperature range. the LTC3255h is guaranteed over the C40c to 150c operating junction temperature range. the LTC3255mp is guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 4: the LTC3255 has an internal diode that conducts whenever v out is pulled below gnd. when so pulled, absolute maximum current out of v out is 50ma. note 5: the LTC3255 has an internal diode that conducts whenever pgood is pulled below gnd. when so pulled, absolute maximum current out of pgood is 100a. note 6: this ic has overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 7: this ic has input overvoltage protection that shuts down the device whenever v in exceeds the specified input voltage range. shutdown typically occurs when v in exceeds 52v. v in subsequently must fall below 50v (typical) for the ic to re-enable. ltc 3255 3255f for more information www.linear.com/LTC3255
4 typical performance characteristics fb pin regulation voltage vs input voltage (i out = 1ma) fb pin regulation voltage vs input voltage (i out = 50ma) fb pin regulation voltage vs temperature operating mode transition voltage vs input voltage (i out = 5ma) operating mode transition voltage vs input voltage (i out = 50ma) typical minimum v in C 2 ? v out compliance required for shunt mode operation input operating current vs input voltage input operating current vs temperature input shutdown current vs input voltage t a = 25c, unless otherwise noted. v in (v) 5 0 i vin (a) 5 15 20 25 50 35 15 25 30 50 3255 g01 10 40 45 30 10 20 35 40 45 shunt = gnd v out = 5v t a = 25c temperature (c) ?60 0 i vin (a) 5 15 20 25 50 35 0 60 90 120 3255 g02 10 40 45 30 ?30 30 150 v in = 12v v out = 5v shunt = gnd v in (v) 0 0 i vin (a) 5 10 15 20 30 10 20 30 40 3255 g03 50 60 150c 25 en = gnd 125c ?55c 25c v in (v) 5 v fb (v) 1.200 1.208 1.216 1.224 25 3255 g04 1.192 1.184 1.196 1.204 1.212 1.220 1.188 1.180 1.176 10 15 20 30 35 40 45 50 i out = 1ma v out = 5v shunt = gnd ?60c 25c 105c 150c v in (v) 5 v fb (v) 1.200 1.208 1.216 1.224 25 3255 g05 1.192 1.184 1.196 1.204 1.212 1.220 1.188 1.180 1.176 10 15 20 30 35 40 45 50 i out = 50ma v out = 5v shunt = gnd ?60c 25c 105c temperature (c) ?60 v fb (v) 1.192 1.216 1.220 1.224 0 60 90 3255 g06 1.184 1.208 1.200 1.188 1.212 1.176 1.180 1.204 1.196 ?30 30 120 150 v in = 12v i out = 1ma v out = 5v v out (v) 2 v in (v) 17 21 25 10 3255 g07 13 9 15 19 23 11 7 5 4 6 8 3 11 5 7 9 12 shunt = gnd 2:1 mode 1:1 mode transition region ? v out (v) 2 v in (v) 17 21 25 10 3255 g08 13 9 15 19 23 11 7 5 4 6 8 3 11 5 7 9 12 shunt = gnd 2:1 mode 1:1 mode transition region ? temperature (c) ?60 2.5 v in C 2 ? v out (v) 2.6 2.8 2.9 3.0 3.5 3.2 0 60 90 120 3255 g09 2.7 3.3 3.4 3.1 ?30 30 150 i vin = 20ma v out = 2.5v v out = 3.3v v out = 5v v out = 12v ltc 3255 3255f for more information www.linear.com/LTC3255
5 v in (v) 4 4.90 v out (v) 4.92 4.96 4.98 5.00 5.10 5.04 6 8 9 3255 g14 4.94 5.06 5.08 5.02 5 7 10 11 15 12 13 14 ?60c 25c 125c shunt = gnd i out = 50ma v in (v) 10 11.75 v out (v) 11.80 11.90 11.95 12.00 12.25 12.10 14 18 20 3255 g15 11.85 12.15 12.20 12.05 12 16 22 24 3026 28 ?60c 25c 125c shunt = gnd i out = 50ma typical performance characteristics output ripple load transient 2.5v output voltage vs falling input voltage 5v output voltage vs falling input voltage 3.3v output voltage vs falling input voltage 12v output voltage vs falling input voltage 3.3v out efficiency vs input voltage at 50ma load 5v out efficiency vs input voltage at 50ma load 5v out efficiency vs output current t a = 25c, unless otherwise noted. v out 20mv/div ac-coupled 40s/div 3255 g10 v in = 12v v out = 3.3v i out = 5ma v out 50mv/div ac-coupled 50ma 5ma i out 40s/div 3255 g11 v in = 12v v out = 3.3v v in (v) 2 2.45 v out (v) 2.46 2.48 2.49 2.50 2.55 2.52 4 6 7 3255 g12 2.47 2.53 2.54 2.51 3 5 8 9 10 ?60c 25c 125c shunt = gnd i out = 50ma v in (v) 2 3.20 v out (v) 3.22 3.26 3.28 3.30 3.40 3.34 4 6 7 3255 g13 3.24 3.36 3.38 3.32 3 5 8 9 1210 11 ?60c 25c 125c shunt = gnd i out = 50ma input voltage (v) 4 efficiency (%) 60 70 80 20 3255 g16 50 40 30 10 8 12 16 6 10 14 18 20 100 90 shunt = gnd ideal ldo LTC3255 input voltage (v) 5 10 efficiency (%) 20 40 50 60 17 19 21 23 100 3255 g17 30 7 9 11 13 15 25 70 80 90 shunt = gnd ideal ldo LTC3255 output current (ma) 0.1 40 30 efficiency (%) power loss (mw) 80 90 1 10 100 3255 g18 70 60 50 20 0 100 120 efficiency power loss v in = 12v 80 60 40 ltc 3255 3255f for more information www.linear.com/LTC3255
6 pin functions c + (pin 1): flying capacitor positive connection. this pin must not be driven externally. v out (pin 2): charge pump output voltage. fb (pin 3): feedback pin for setting the regulated output voltage, usually connected to v out through an external resistor divider. in operation, the LTC3255 servos the fb pin to 1.2v by transferring charge from v in to v out . shunt (pin 4): configuration pin that must connect to either the bias or gnd pins to enable or defeat, respec- tively, the LTC3255s shunt regulator feature. connect this pin to either bias or gnd on the circuit board layout. do not float this pin. pgood (pin 5): power good open-drain logic output. this pin becomes high impedance when the feedback voltage on the fb pin rises above 94% ( typical) of the regulation voltage . en (pin 6): logic input. a logic high on the en pin will enable the charge pump. a logic low shuts down the LTC3255. do not float this pin. bias (pin 7): connect this pin to a 0.1f bypass capaci- tor to gnd. a ceramic capacitor of at least 10v rating is recommended. gnd (pin 8 and exposed pad pin 11): ground connection . exposed pad (pin 11) must be soldered to the circuit board ground plane for proper thermal and electrical conduction . c C (pin 9): flying capacitor negative connection. this pin must not be driven externally. v in (pin 10): input supply voltage . bypass this pin to gnd with at least 1f capacitance. ltc 3255 3255f for more information www.linear.com/LTC3255
7 simplified block diagram 1 2 c + v out 11 fb 1.2v 7 bias 9 c ? 4 shunt 6 en 5 pgood 10 v in shunt control charge pump control internal biasing 1.13v 3255 bd gnd 8 gnd ? + ? + 3 ltc 3255 3255f for more information www.linear.com/LTC3255
8 applications information general operation the LTC3255 uses switched - capacitor - based dc/ dc conversion to provide efficiency advantages associated with inductor-based circuits together with the cost and simplicity advantages of linear regulators. no inductors are required . the ltc 3255 uses an internal switch network and fractional conversion ratios to achieve high efficiency and regulation over widely varying v in and output load conditions. a defeatable v in shunt regulator allows the LTC3255 to operate with current-fed v in supplies, such as 4ma to 20ma current loops. automatic 2:1/1:1 mode switching with v in shunt disabled (shunt pin connected to gnd) connecting the shunt pin to gnd defeats the v in shunt regulator. with the shunt regulator defeated, the LTC3255 functions as a general purpose step-down charge pump offering two conversion modes: 2:1 and 1:1. internal cir - cuitry automatically chooses the optimal conversion ratio based on v in , v out , and output load conditions, generally preferring 2:1 mode when v in exceeds twice v out , but falling back to 1:1 mode as needed to maintain regulation. forced 2:1 mode operation when v in shunt regulator is enabled (shunt pin connected to bias) with the shunt pin connected to bias, the v in shunt regulator is enabled, and the LTC3255 expects a high impedance power source at v in , such as a 4ma to 20ma current loop, or a resistor to a dc supply. with the shunt regulator enabled, the charge pump runs in 2:1 conversion mode only, extending its output current capability beyond that of the v in source . for example, the LTC3255 can typically boost the current capability of a 4ma source to power a 7.4ma load continuously. see v in shunt regula- tor in the operation section for v in compliance and other operating information. regulation loop regulation is achieved via a burst mode control loop that allows the LTC3255 to achieve high efficiency even at light loads. as shown in the block diagram, a comparator monitors the output voltage via a feedback pin, fb, which receives a fraction of v out via an external resistor divider. while v fb is below regulation, the LTC3255 transfers fixed packets of charge from v in to v out , paced by an internal oscillator. this causes v out and hence fb to rise. when v fb enters regulation, the LTC3255 stops charge transfer and enters a low quiescent current sleep state. during this sleep state , the output load is supplied entirely by the output capacitor. the LTC3255 remains in sleep until the output drops enough to require another burst of charge. as load current decreases, the output capacitor takes longer to discharge, so sleep time increases. shutdown and undervoltage lockout (uvlo) driving the en pin low puts the LTC3255 in shutdown, which disables all circuitry except the internal bias. v in supply current is minimized. when the en pin is high, the charge pump will enable if v in satisfies the v in undervolt - age lockout (uvlo) threshold. if the shutdown feature is not needed, the en pin can be connected to v in , as both pins share the same absolute maximum rating. reverse polarity input protection the v in and en pins are designed to withstand connection to voltages below ground without damage. when v in is below ground , the ltc 3255 prevents v out from going more than a diode drop below gnd to protect the load circuit. short-circuit/thermal protection the LTC3255 has built-in short- circuit current limiting as well as overtemperature protection. during short- circuit conditions output current is automatically limited by the output current limit circuitry. ltc 3255 3255f for more information www.linear.com/LTC3255
9 applications information the LTC3255 has thermal protection that will shut down the device if the junction temperature exceeds the overtemperature threshold ( typically 175 c ). thermal shutdown is included to protect the ic in cases of exces- sively high ambient temperatures, or in cases of excessive power dissipation inside the ic. the charge transfer will reactivate once the junction temperature drops back to approximately 165c. when the thermal protection is active, the junction tem- perature is beyond the specified operating range. thermal protection is intended for momentary overload conditions outside normal operation. continuous operation above the specified maximum operating junction temperature may impair device reliability. programming the output voltage (fb pin) the LTC3255 output voltage is set by connecting its fb pin to a resistor divider between v out and gnd as shown in figure 1. the desired adjustable output voltage is programmed by solving the following equation for r a and r b : r a r b = v out 1.2v C 1 select a value for r b in the range of 20k to 2m and solve for r a . note that the resistor divider current adds to the total no-load operating current. thus a larger value for r b will result in lower operating current. 2:1 step-down charge pump operation in 2:1 step-down mode, charge transfer from v in to v out happens in two phases. on the first phase, the flying ca- pacitor (c f ly ) is connected between v in and v out . on this phase c f ly is charged up and current is delivered to v out . on the second phase, c f ly is connected between v out and gnd. the charge stored on c f ly during the first phase is transferred to v out on the second phase. when in 2:1 step-down mode, the input current will be approximately half of the total output current. the efficiency () and chip power dissipation (p d ) in 2:1 mode are approximately: = p out p in = v out ?i out v in ? 1 2 i out = 2v out v in p d = v in 2 C v out ? ? ? ? ? ? i out 1:1 step-down charge pump operation 1:1 step-down mode is similar to how a linear regulator works. charge is delivered directly from v in to v out through most of the internal oscillator period. the charge transfer is briefly interrupted at the end of the period. when in 1:1 step-down mode the input current will be approximately equal to the total output current. thus efficiency () and chip power dissipation ( p d ) in 1:1 mode are approximately : = p out p in = v out ?i out v in ?i out = v out v in p d = v in C v out ( ) i out v out fb r a c out 3255 f01 v out = r b gnd LTC3255 1.2v 1 + ( ) r a r b figure 1. setting the output voltage ltc 3255 3255f for more information www.linear.com/LTC3255
10 applications information power good output operation (pgood) the ltc 3255 includes an open - drain power good ( pgood ) output pin. if the chip is in shutdown or undervoltage lockout, or if the fb pin voltage is less than 90% (typi- cal) of its regulation voltage, pgood is low impedance to ground. pgood becomes high impedance when v out rises to 94% (typical) of its regulation voltage. pgood stays high impedance until v out is shut down or drops below the pgood falling threshold (90% typical). a pull- up resistor can be inserted between pgood and v out to signal a valid power good condition. the use of a large value pull-up resistor on pgood and a capacitor placed between pgood and gnd can be used to delay the pgood signal if desired. v in shunt regulator operation the v in shunt regulator feature of the LTC3255 is intended for applications where v in is current-fed, such as in 4ma to 20ma current loops. a circuit powered by a current loop must limit the voltage drop it presents to the loop to avoid exceeding the loop compliance, which would break the current loop. the LTC3255s v in shunt regulator moni- tors v in and v out , drawing v in current as necessary to keep v in from rising much beyond 3v above twice v out . the shunt regulator is enabled by connecting the shunt pin to the bias pin in the circuit board layout. the shunt is disabled by connecting the shunt pin to gnd. the shunt regulator dissipates power which must be ac- counted for in thermal budgeting. total power dissipation (p dshunt ) in the ltc 3255 with shunt regulator enabled is equal to the input power minus the output power of the LTC3255, or approximately: p d(shunt) = p in Cp out = v in ?i in C v out ?i out 2 ? v out + 2v ( ) ?i in C v out ?i out where i in is the time-averaged current being fed into v in by the current loop, v out is the output voltage, and i out is the output load current. notice that the largest power dissipation occurs when output load current is zero. this is because any power fed into v in must be dissipated in either the load or the LTC3255. if the load is not drawing any current, then the LTC3255 must dissipate all of the input power. when the shunt regulator is enabled, the LTC3255 charge pump is locked in 2:1 mode. to achieve output regulation, the input current to the part must have sufficient voltage compliance above twice v out . the graph in figure 2 shows the typical minimum compliance required at the v in pin for correct operation. for v out 5.5 v, a v in compliance of 2v out + 3.5v is recommended. for v out > 5.5v, a v in compliance of 2v out + 4v is recommended. temperature (c) ?60 2.5 v in C 2 ? v out (v) 2.6 2.8 2.9 3.0 3.5 3.2 0 60 90 120 3255 f02 2.7 3.3 3.4 3.1 ?30 30 150 i vin = 20ma v out = 2.5v v out = 3.3v v out = 5v v out = 12v figure 2. typical minimum v in C 2 ? v out compliance required for shunt mode operation ltc 3255 3255f for more information www.linear.com/LTC3255
11 applications information v out ripple and capacitor selection the type and value of capacitors used with the LTC3255 determine several important parameters such as output ripple and charge pump strength. the value of c out directly controls the amount of output ripple for a given load current. increasing the size of c out will reduce the output ripple. to reduce output noise and ripple, it is suggested that a low esr (equivalent series resistance < 0.1) ceramic capacitor (10f or greater) be used for c out . ceramic capacitors typically have exceptionally low esr which, combined with a tight board layout, should yield excellent performance . tantalum and aluminum capacitors can be used in parallel with a ceramic capacitor to increase the total capacitance but are not recommended to be used alone because of their high esr. v in capacitor selection the total amount and type of capacitance necessary for input bypassing is very dependent on the impedance of the input power source as well as existing bypassing al- ready on the v in node. for optimal input noise and ripple reduction, it is recommended that a low esr ceramic capacitor be used for c in bypassing. low esr will reduce the voltage steps caused by changing input current, while the absolute capacitor value will determine the level of ripple. an electrolytic or tantalum capacitor may be used in parallel with the ceramic capacitor on c in to increase the total capacitance, but due to the higher esr, it is not recommended that an electrolytic or tantalum capacitor be used alone for input bypassing. the LTC3255 will operate with capacitors less than 1f, but depending on the source impedance, input noise can feed through to the output causing degraded performance . for best performance , 1f or greater total capacitance is suggested for c in . flying capacitor selection the flying capacitor should always be a ceramic type. polarized capacitors such as tantalum or aluminum electro - lytics are not recommended. the flying capacitor controls the strength of the charge pump. in order to achieve the rated output current, it is necessary for the flying capaci- tor to have at least 0.4f of capacitance over operating temperature with a bias voltage equal to the programmed v out (see ceramic capacitor selection guidelines). the voltage rating of the ceramic capacitor should be v out + 1v or greater. ceramic capacitor selection guidelines capacitors of different materials lose their capacitance with higher temperature and voltage at different rates. for example, a ceramic capacitor made of x5r or x7r material will retain most of its capacitance from C40c to 85c, whereas a z5u or y5v style capacitor will lose considerable capacitance over that range (60% to 80% loss typical). z5u and y5v capacitors may also have a very strong voltage coefficient, causing them to lose an additional 60% or more of their capacitance when the rated voltage is applied. therefore, when comparing different capacitors, it is often more appropriate to compare the amount of achievable capacitance for a given case size rather than discussing the specified capacitance value. for example, over rated voltage and temperature conditions, a 4.7f, 10v, y5v ceramic capacitor in an 0805 case may not provide any more capacitance than a 1f, 10v, x5r or x7r available in the same 0805 case. in fact, over bias and temperature range, the 1f, 10v, x5r or x7r will provide more capacitance than the 4.7f, 10v, y5v. the capacitor manufacturers data sheet should be consulted to determine what value of capacitor is needed to ensure minimum capacitance values are met over operating temperature and bias voltage. table 1 is a list of ceramic capacitor manufacturers in alphabetical order: ltc 3255 3255f for more information www.linear.com/LTC3255
12 applications information table 1 ceramic capacitor manufacturer website avx www.avxcorp.com kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com tdk www.tdk.com layout considerations due to the high switching frequency and transient cur - rents produced by the LTC3255, careful board layout is necessary for optimal performance . a true ground plane and short connections to all capacitors will optimize performance , reduce noise and ensure proper regulation over all conditions. when using the LTC3255 with an external resistor divider it is important to minimize any stray capacitance to the fb node. stray capacitance from fb to c + or c C can degrade performance significantly and should be minimized and/ or shielded if necessary. thermal management the on chip power dissipation in the LTC3255 will cause the junction to ambient temperature to rise at a rate of 40 c/w or more in the mse package, or 43c/w or more in the dd package. to reduce the maximum junction temperature, a good thermal connection to the pc board is recommended. connecting the die paddle (pin 11) to a large ground plane under the device can reduce the thermal resistance of the package and pc board considerably . poor board layout and failure to connect the die paddle (pin 11) to a large ground plane can result in thermal junction to ambient impedance well in excess of 40c/w ( mse package) or in excess of 43c/w (dd package). thermal junction to ambient impedance is specified per jedec standard jesd 51-5. because of the wide input operating range it is possible to exceed the specified operating junction temperature and even reach thermal shutdown. it is the responsibility of the user of the LTC3255 to calculate worst-case operat- ing conditions (temperature and power) to make sure the LTC3255s specified operating junction temperature is not exceeded for extended periods of time. the 2:1 step-down, 1:1 step-down, and v in shunt regulator operation sections provide equations for calculating the power dissipation (p d ) in each mode. for example, if it is determined that the maximum power dissipation (p d ) is 1.2w under normal operation, then the maximum junction to ambient temperature rise in the mse package will be: junction to ambient = 1.2w ? 40c/w = 48c thus, the ambient temperature under this condition can not exceed 102c if the junction temperature is to remain below 150 c . for ambient temperatures exceeding roughly 127c, the device will cycle in and out of the thermal shutdown. ltc 3255 3255f for more information www.linear.com/LTC3255
13 typical applications wide input range 5v microcontroller supply (with power-on reset delay) v in en 383k 10f 1f v out = 5v 3255 ta02 0.1f input 6v to 48v 1f 1f LTC3255 gnd c + c ? bias shunt fb pgood v out 510k 121k v dd gnd reset controller v in en 383k 121k 10f 3255 ta03 0.1f 4ma to 20ma input 13.5v compliance 1f 1f output 5v 7ma LTC3255 gnd c + c ? bias shunt fb + ? pgood pgood v out 220k 7 ma 5v supply from 4ma to 20ma current loop ltc 3255 3255f for more information www.linear.com/LTC3255
14 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer ltc 3255 3255f for more information www.linear.com/LTC3255
15 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (mse) 0213 rev i 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev i) ltc 3255 3255f for more information www.linear.com/LTC3255
16 ? linear technology corporation 2013 lt 0813 ? printed in usa related parts typical application wide input range 12v supply v in en 1.1m 121k 10f 3255 ta04 0.1f input 13v to 48v 1f 1f output 12v 50ma LTC3255 gnd c + c ? bias shunt fb pgood pgood v out 220k part number description comments ltc1751-3.3/ltc1751-5 100ma, 800khz regulated doubler v in : 2v to 5v, v out(max) = 3.3v/5v, i q = 20a, i sd < 2a, ms8 package ltc1983-3/ltc1983-5 100ma, 900khz regulated inverter v in : 3.3v to 5.5v, v out(max) = C3v/C5v, i q = 25a, i sd < 2a, thinsot? package ltc3200-5 100ma, 2mhz low noise, doubler/white led driver v in : 2.7v to 4.5v, v out(max) = 5 v, i q = 3.5ma, i sd < 1a, thinsot package ltc3202 125ma, 1.5mhz low noise, fractional white led driver v in : 2.7v to 4.5v, v out(max) = 5.5v, i q = 2.5ma, i sd < 1a, dfn, ms packages ltc3204-3.3/ltc3204b-3.3 ltc3204-5/ltc3204b-5 low noise, regulated charge pumps in (2mm 2mm) dfn package v in : 1.8v to 4.5v (ltc3204b-3.3), 2.7v to 5.5v (ltc3204b-5), i q = 48a, ltc3204b version without burst mode operation, 6-lead (2mm 2mm) dfn package ltc3440 600ma (i out ) 2mhz synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25a, i sd 1a, 10-lead ms package ltc3441 high current micropower 1mhz synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25a, i sd 1a, dfn package ltc 3443 high current micropower 600khz synchronous buck-boost dc/dc converter 96% efficiency, v in : 2.4v to 5.5v, v out(min) = 2.4v, i q = 28a, i sd < 1a, dfn package ltc3240-3.3/ ltc3240-2.5 3.3v/2.5v step-up/step-down charge pump dc/dc converter v in : 1.8v to 5.5v, v out(max) = 3.3v/2.5v, i q = 65a, i sd < 1a, (2mm 2mm) dfn package ltc3245 wide v in range low noise 250ma buck-boost charge pump v in : 2.7v to 38v, v out(max) = 5v, i q = 20a, i sd = 4a, 12-lead ms and (3mm 4mm) dfn packages ltc3260 low noise dual supply inverting charge pump inverting charge pump with integrated dual polarity 50ma ldo post-regulated outputs. v in : 4.5v to 32v, charge pump v out : C0.94 ? v in , 100ma ltc3261 high voltage, low quiescent current inverting charge pump v in : 4.5v to 32v, v out = Cv in , i out = 100ma, msop-12 package linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3255 ltc 3255 3255f for more information www.linear.com/LTC3255

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